A wafer containing numerous integrated circuits, will generally include at least two conductive (or semi-conductive) layers, one lying above the other and separated by an insulator, and with the layers interconnected at numerous interfaces. High resistance at such interfaces is a major source of defects. One way to measure interface resistance is to form one or more contact chains on the wafer, at locations adjacent to some or all of the integrated circuits. Each contact chain has many conductive segments formed in each layer, and the conductive segments are connected in series by interfaces between the layers. A pair of tabs is provided at opposite ends of a chain containing the many interfaces in series, and the resistance between the tabs is measured. While this can indicate the existance of a catastrophic failure (a very high resistance interface), it does not provide information as to the resistence at each of the many interfaces.
The detection of the resistance at each of several interfaces can be made by providing four pairs of terminals or tabs for each interface. Current can pass between a first pair of tabs while the voltage is measured across the other pair of tabs, to determine the resistance across that interface. However, the need for a large number of tabs such as 44 tabs for testing 11 interfaces, gives rise to the problem that there may not be sufficient room on the wafer for so many tabs. A system which facilitated the measurement of resistance across each of numerous interfaces while minimizing the number of tabs required, and simplified the test instrument requirements, would facilitate the testing of integrated circuits. The utilization of such interface measurements to predict the yield of integrated circuits, would be of further value.